Analyzing the Performance of NoC Using Hierarchical Routing Methodology

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ABSTRACT:  The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporating any number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device, long interconnection should be avoided. For that, new interconnect patterns are needed. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing the total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.

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