FIR Filter Design Using Floating point Column Bypassing Technique

M.E Project:

Phase-1:

Title:  Analysis, Design and Implementation of 4-Bit Full Adder using FinFET

Summary: This project proposed a 4-Bit full adder using FinFET at 45nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Sub threshold swing, channel length modulation, mobility degradation etc. To replace nanoscale CMOS, a multi gate device called FinFET is proposed. FinFET has its own advantages over the CMOS such as reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this project is to reduce and calculate leakage power of 4-Bit full adder using FinFET. The following graph is the output of the 4 bit full adder.

 

Phase-2:

Title: Analysis, Design and Implementation of 4-Bit ALU using FinFET

Summary: This project proposed a 4-Bit ALU (Arithmetic and Logic Unit) using FinFET at 45nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Sub threshold swing, channel length modulation, mobility degradation etc. To replace nanoscale CMOS, a multi gate device called FinFET is proposed. FinFET has its own advantages over the CMOS such as reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. In this project, the ALU circuit was designed by both, CMOS and FinFET technologies and then compared the results. The following graph is the output of the 4 bit ALU.

Sub-Project -1:

Aim: To design ALU circuit and 4×1 Multiplexer using Encounter digital flow (Cadence Virtuoso- Encounter to GDSII).

Summary: The Encounter digital flow allows to route the ALU circuit and multiplexer circuit, such as local routing, area routing, channel routing and global routing. To determine time design summary, clock tree synthesize, LVS and DRC encounter flow used. To create path for power rings, floor planning will be done. The below diagram explains the encounter flow of the particular circuit.

Sub-Project – 2:

Aim: Error Detection and Correction Using TURBO Code with Interleaving in FEC Channel
Summary: In telecommunication, forward error correction (FEC) or channel coding is a technique used for governing errors in data transmission in the communication channel. FEC tends to discover the errors and correct them. The various coding methods that can be employed are achieved by interweaving additional binary digits into transmission. When decoded on receiving end, the transmission can be checked for errors that may have occurred and, in many cases, repaired. In this project, the errors are detect and corrected by TURBO codes. TURBO code belongs to convolutional code (with memory) group. TURBO code outperforms all previously known coding schemes by achieving near Shannon limit error correction using simple component codes and large interleavers. The output waveform of the interleavers can be shown below.

 TURBO codes are used as channel coding which has the ability to detect and correct errors that present in the channel. So it can avoid use of extra channel bandwidth for retransmission and also economical. TURBO codes are used in 3G mobile communications and satellite communication as well as other application. TURBO codes are a recent development in the field of forward error correction channel coding. This codes make use of three simple ideas parallel concatenation of codes to allow simpler decoding; interleaving to provide better weight distribution; and soft decoding to enhance decoder decisions and maximize the gain from decoder.