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B.Tech Project:
Title: Investigation of Nano-scale FinFETs for Memories
Summary:  According to International Technology Road map for Semiconductors (ITRS) by the year 2013, 94%of the chip is occupied by the memory devices. A FinFET is an intrinsic body which will greatly suppresses the device-performance variability caused by the fluctuation in the number of dopant ions. Heavy doping reduces mobility due to impurity scattering and a high transverse electric field in the on state worsens sub-threshold swing and increases parasitic junction capacitance. FinFETs are alternatives to bulk FETs due to their stronger electrostatic control over the channel which have improved short channel behavior. The given below figure represent the general 3D structure of FinFET.
        With SOI wafer as a basic platform, a thin film of silicon having thickness TSI is patterned on it. The gate shawls around the fin. The channel is formed perpendicular to the plane of the wafer. Its length is shown as LG. This is the reason that the device is termed quasi-planar. The effective width of a FinFET is 2nHfin , where ‘n’ is the number of fins and Hfin is the fin height. Multiple fins are used to made a high on-current transistors. FinFET width is quantized, in terms of number of fins. Some key design factors like performance, power and functionality, profound on β ratio are also dealt

           My UG project was analyzing the performance of FinFETs by using different types of materials (silicon, poly-silicon, nitride, etc.,) in the gate for different kinds of technology. And found that for which material of the FinFET, the performance has been improved. The device modeling is done with the help of Synopsys TCAD Software. The above snapshot shows that the modeling of FinFET using TCAD sentauras software. 

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