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International Conference Attended (2)

[1]   International Conference:
 International Conference on Advances in Emerging Technologies on 28.03.2015
 Paper Title: Improving the Performance of NoC Using Hierarchical Routing   
 Methodology

[2]   International Conference:
      International Conference on Emerging Trends in the Information & Communication Technologies on 27th April, 2016.
      Paper Title: Error Detection and Correction Using TURBO CODE with Interleaving in
      FEC Channel

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I obtained B.Tech (ECE) from the department of Electronics and Communication, Karunya University and got M.E degree (VLSI Design) from Vel Tech Multi Tech Engineering College, Anna University. Now I am pursuing a PhD (ICE) at Anna University. As a VLSI engineer, it is a challenge to do the computation even faster and even more economical. It’s inspired me to do some research, in the field of DSP applications like MAC (multiplier-accumulator), filtering, and convolution. And other interesting fields are Nanoscale device modelling and simulation such as FinFET, CNFET, and TFET technology and also, optimize the VLSI circuits. Moreover, I have a special interest in Number Theory system, particularly the Residue Number system and Logarithmic Number system for the Floating-point arithmetic computation.  I have participated in some of the International conferences and published some papers in the refereed and SCI-indexed journals. I am a recognized peer-reviewer of the SAGE...
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ABSTRACT:   This paper presents the design of floating-point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in an FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software. Index Terms: Column bypassing technique, error reduction algorithms, FIR filter, Fixed-width multiplier, nearest rounding, wrap overf...
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