Paper Publications (3) [1] Journal Name: “ Journal of Convergence Information Technology ” published in ISSN: 1975-9320 Volume 10 Number2 March 2015. Paper Title: Analysis, Design and Implementation of 4 bit Full Adder Using FinFET [2] Journal Name: “ International Journal of Emerging Technology in Computer Science and Electronics ” published in ISSN:0976-1353 Volume 13 Issue 4- March 2015 Paper Title: Improving the Performance of NoC Using Hierarchical Routing Methodology [3] Journal Name: “ International Journal of Engineering Research and Applications ” published in ISSN: 2248-9622, Vol. 5, Issue 12, (Part - 1) December 2015. Paper Title: Review of Fin FET Technology and Circuit Design Challenges
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International Conference Attended (2) [1] International Conference: International Conference on Advances in Emerging Technologies on 28.03.2015 Paper Title: Improving the Performance of NoC Using Hierarchical Routing Methodology [2] International Conference: International Conference on Emerging Trends in the Information & Communication Technologies on 27 th April, 2016. Paper Title: Error Detection and Correction Using TURBO CODE with Interleaving in FEC Channel
Workshop Attended (9) [1] Attended workshop programme on ROBOTICS-ROBO TOUCH , ABLab Solutions organized by Karunya University on 4 th & 5 th March 2011. [2] National level workshop and hands-on-training on DIGITAL IC DESIGN USING CADENCE EDA , Vel Tech Multi Tech Engineering College on o4, April 2014 . [3] Workshop on ADVANCED NANO-SCALE DEVICE DESIGN USING TCAD , VIT Chennai on 9 th May 2014. [4] Presented Seminar topic entitled “ Fixed Width Parallel Multiplier-Accumulator based on Higher Radix Algorithm ” in the Faculty Research Day held on 17 th Aril, 2015 at Sri Venkateswara College of Engineering. [5] Participated in the one day workshop on “ Academic Writing in Refereed Journals and ...
PhD Project (On going): Title : Performance Analysis and application of Carbon Nanotube FET Abstract : The main aim of the IC manufacturing companies is miniaturization without sacrificing their performance. Recently carbon nanotube field effect transistor (CNFET), which has short channel effect, is the other opinion. CNFET is better results than CMOS and FinFET technologies in terms of power consumption. In this project Arithmetic and Logic Unit is designed using CNFET 32 nm technology and going to analyze some characteristics of that device.
M.E Project: Phase-1: Title: Analysis, Design and Implementation of 4-Bit Full Adder using FinFET Summary: This project proposed a 4-Bit full adder using FinFET at 45nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Sub threshold swing, channel length modulation, mobility degradation etc. To replace nanoscale CMOS, a multi gate device called FinFET is proposed. FinFET has its own advantages over the CMOS such as reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this project is to reduce and calculate leakage power of 4-Bit full adder using FinFET. The following graph is the output of the 4 bit full adder. Phase-2: Title: Analysis, Design and Implementation of 4-Bit ALU using FinFET Summary: This project proposed a 4-Bit ALU (Arithmetic and Logic Unit)...
B.Tech Project: Title: Investigation of Nano-scale FinFETs for Memories Summary: According to International Technology Road map for Semiconductors (ITRS) by the year 2013, 94%of the chip is occupied by the memory devices. A FinFET is an intrinsic body which will greatly suppresses the device-performance variability caused by the fluctuation in the number of dopant ions. Heavy doping reduces mobility due to impurity scattering and a high transverse electric field in the on state worsens sub-threshold swing and increases parasitic junction capacitance. FinFETs are alternatives to bulk FETs due to their stronger electrostatic control over the channel which have improved short channel behavior. The given below figure represent the general 3D structure of FinFET. With SOI wafer as a basic platform, a thin film of silicon having thickness TSI is patterned on it. The gate shawls around the fin. The channel is formed perpendicular to...
I obtained B.Tech (ECE) from the department of Electronics and Communication, Karunya University and got M.E degree (VLSI Design) from Vel Tech Multi Tech Engineering College, Anna University. Now I am pursuing a PhD (ICE) at Anna University. As a VLSI engineer, it is a challenge to do the computation even faster and even more economical. It’s inspired me to do some research, in the field of DSP applications like MAC (multiplier-accumulator), filtering, and convolution. And other interesting fields are Nanoscale device modelling and simulation such as FinFET, CNFET, and TFET technology and also, optimize the VLSI circuits. Moreover, I have a special interest in Number Theory system, particularly the Residue Number system and Logarithmic Number system for the Floating-point arithmetic computation. I have participated in some of the International conferences and published some papers in the refereed and SCI-indexed journals. I am a recognized peer-reviewer of the SAGE...