International Conference: 2nd International Conference on Recent Innovations in Science, Engineering & Technology Paper Title: FIR Filter Design Using Floating point Column Bypassing Technique
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Design and Analysis of Low Power Fixed-Width Multiplier Using Reduced Precision Redundancy Block (RPR)
ABSTRACT: This paper suggests a low power fixed-width multiplier using a reduced precision redundancy unit (RPR) for VLSI signal processing applications. RPR consists of a reduced precision module and a full precision module. The result of the reduced precision is considered as the correct output when the source output computes falsely. The proposed RPR fixed-width multiplier can satisfy the demand for accuracy, area efficiency, processing speed, and low power consumption. The precision of the proposed multiplier will be enhanced by the RPR logic. The compensation bias consists of probability and statistics. To avoid the truncation error many types of rounding methods are employed. The proposed RPR fixed-width multiplier is installed in the FIR filter design for various signal processing applications. The detailed analysis of the suggested multiplier gives 30% power reduction and 46.54% area reduction as compared with the different techniques. Keywords: Fixed-width...
FIR filter design using floating point radix 4 algorithm
ABSTRACT: Digital filters are generally used to vary or modify the features of a signal in the time or frequency domain. The most commonly used digital filter is FIR filter. FIR filter is mainly used in digital signal processing applications such as speech processing, sonar, radar and digital communication. The FIR filter is used to process the input signals by the linear convolution algorithm. It involves a series of addition and multiplication operation. So, the primary building block of the FIR filter is considered as multiply-accumulate (MAC) unit. This paper proposed to use novel floating-point radix 4 algorithms to multiply the input impulse responses. This algorithm helps to enhance the performance of the filter in terms of speed. Various rounding techniques will be used for the filter accuracy. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software. The brief investigation of the fixed a...
FIR Filter Design Using Floating point Column Bypassing Technique
ABSTRACT: This paper presents the design of floating-point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in an FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software. Index Terms: Column bypassing technique, error reduction algorithms, FIR filter, Fixed-width multiplier, nearest rounding, wrap overf...
A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm
ABSTRACT: The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematic...
Design of Low power 4 bit ALU using 32 nm FinFET technology
ABSTRACT: This paper proposes a 4-Bit Arithmetic logic unit (ALU) using FinFET at 32nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Subthreshold swing, channel length modulation, mobility degradation etc. To change nanoscale CMOS, a multi-gate device called FinFET is suggested. FinFET has its own advantages over the CMOS such as the reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this paper is to reduce and calculate the leakage power of 4-Bit ALU using FinFET. Keywords: FinFET technology; Cmos technology; Arith-metic logic unit (ALU); Leakage power; Low power analysis; Delay analysis. To View the Full-text CLICK HERE
Investigation of 6T SRAM Characteristics Using TFET
ABSTRACT: This paper proposes to design and investigate the SRAM memory cell features using TFET in the InAs/GaSb-InAs platform. This platform lies within the type III (Hetero-junction) alignment in TFET. The word TFET symbolizes to the Tunneling Field Effect Transistor which is related to the MOSFET but follows quantum tunnelling switching mechanism. TFET having an advantage over MOSFET such as high speed, energy-efficient and low power applications in the field of integrated circuits. The suggested project is the design of 6T SRAM memory cell with 32nm TFET technology. Finally, the performance estimation of the proposed SRAM has been compared with CMOS, FinFET, and CNFET. The study of the competence of the SRAM cell can be done by Hspice tool and Verilog-A language used. Keywords: Buffer, CMOS, Heterojunction, SRAM read/write, SRAM, TFET. To View the Full-text CLICK HERE
Enhanced Modified Booth Recoding Technique for Signal Processing Application
ABSTRACT: Digital signal processing applications consist of many complex arithmetic operations. The multiplier circuit plays a vital role in the DSP applications. The performance of the DSP processor improved with the efficiency of the multiplier circuit. In this paper, presents enhanced Modified Booth recoding for the optimization of Fused Add Multiply (FAM). The proposed FAM compared with the existing results and it is excellent in the reduction of area, delay and power of the FAM unit. Keywords: Digital Signal Processing, Booth Algorithm, Modified Booth Recording, Fused add multiply (FAM), Multiplexer, Carry Slave adder, Carry Look-ahead adder. To View the Full-text CLICK HERE
Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
ABSTRACT: This paper proposes a 4-Bit full adder using FinFET at 45nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Subthreshold swing, channel length modulation, mobility degradation etc. To replace nanoscale CMOS, a multi-gate device called FinFET is proposed. FinFET has its own advantages over the CMOS such as the reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this paper is to reduce and calculate the leakage power of 4-Bit full adder using FinFET. Keywords: 4-Bit full adder, FinFET, Circuit designing, Device simulation, Device Modeling, CMOS Integrated Circuit, Low Power To View the Full-text CLICK HERE Keywords : 4-Bit full adder, FinFET, Circuit designing, Device simulation, Device Modeling, CMOS Integrated Circuit, Low Power Keywords : ...
Analyzing the Performance of NoC Using Hierarchical Routing Methodology
ABSTRACT: The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporating any number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device, long interconnection should be avoided. For that, new interconnect patterns are needed. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing the total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software. To View the Full-text CLICK HERE
Review of FinFET Technology and Circuit Design Challenges
ABSTRACT: Considering the difficulties in planar CMOS transistor scaling to secure an acceptable gate to channel control FinFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the existing technology. The desirability of FinFET that its operation principle is the same as CMOS process. This permits to lengthening the gate scaling beyond the planar transistor limits, sustaining a steep subthreshold slope, better performance with bias voltage scaling and good matching due to low doping concentration in the channel. There are, still, several challenges and limitations that FinFET technology has to face to be competitive with other technology options: Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as device parasitic, performance and patterning approaches will be discussed. To View the Full-text CLICK HERE