Posts

Jency Rubia J

I obtained B.Tech (ECE) from the department of Electronics and Communication, Karunya University and got M.E degree (VLSI Design) from Vel Tech Multi Tech Engineering College, Anna University. Now I am pursuing a PhD (ICE) at Anna University. As a VLSI engineer, it is a challenge to do the computation even faster and even more economical. It’s inspired me to do some research, in the field of DSP applications like MAC (multiplier-accumulator), filtering, and convolution. And other interesting fields are Nanoscale device modelling and simulation such as FinFET, CNFET, and TFET technology and also, optimize the VLSI circuits. Moreover, I have a special interest in Number Theory system, particularly the Residue Number system and Logarithmic Number system for the Floating-point arithmetic computation.  I have participated in some of the International conferences and published some papers in the refereed and SCI-indexed journals. I am a recognized peer-reviewer of the SAGE...
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International Conference: 2nd International Conference on Recent Innovations in Science, Engineering & Technology Paper Title: FIR Filter Design Using Floating point Column Bypassing Technique
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International Conference: SITAMS International Conference on Innovations in Engineering, Technology and Science Paper Title: Investigation of 6T SRAM Characteristics Using TFET
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IEEE International Conference: 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017) Paper Title: A Survey Paper on Modern Technologies in Fixed-Width Multiplier To View the Full-text   CLICK HERE
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International Conference: International Conference on Innovative Techniques in Science, Engineering & Information Technology Paper Title: Design of Low power 4 Bit ALU Using 32 nm FinFET Technology.
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International Conference: International Conference on Trends in Engineering with Computation Hikes Paper Title: Enhanced Modified Booth Recoding Technique for Signal Processing Application
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IEEE Sponsored International Conference: International Conference on Engineering and Technology Paper Title: Performance Investigation of a Full Adder using CNFET Technology To View the Full-text   CLICK HERE